Generally, a broadcast receiver is constituted by a high-frequency receiving circuit and a demodulation circuit, and a broadcast transmitter is constituted by a high-frequency transmitting circuit and a modulation circuit. Although the following will describe a case of a broadcast receiver, the same is applied to a broadcast transmitter.
A high-frequency receiving circuit of a broadcast receiver is generally constituted by an analog circuit, serving as an analog semiconductor integrated circuit. On the contrary, a demodulation circuit is generally constituted by a logic circuit, serving as a logic semiconductor integrated circuit. Since the high-frequency receiving circuit and the demodulation circuit are significantly different from each other regarding their circuit configurations, generally, they have been manufactured as independent semiconductor chips. In recent years, with the development of semiconductor processing techniques, the analog semiconductor integrated circuit and the logic integrated circuit are realized on a single chip.
When such a broadcast receiver is tested, the high-frequency receiving circuit and the demodulation circuit are tested separately. This is because there are significant differences between the demodulation circuit serving as a logic circuit and the high-frequency receiving circuit serving as an analog circuit, with regard to what and how they are tested.
FIG. 8 is a block diagram illustrating a structure in which a semiconductor integrated circuit 92 and a semiconductor test device 77 are provided. The semiconductor integrated circuit 91 includes a high-frequency receiving circuit 92 and a demodulation circuit 93. The high-frequency receiving circuit 92 includes a variable gain amplifier 99. The variable gain amplifier 99 amplifies a high-frequency signal (hereinafter referred to as RF signal), and provides it to a mixer circuit 80.
The high-frequency receiving circuit 92 includes a voltage controlled oscillator (hereinafter referred to as VCO) 81. The VCO 81 generates an oscillation signal that oscillates at a specific frequency, and provides the signal to a phase locked loop circuit (hereinafter referred to as PLL) 82 and a 90 degree phase shifter 84. The PLL circuit 82 locks a phase of the oscillation signal received from the VCO 81, and outputs the signal to a loop filter 83. The loop filter 83 receives the signal from the PLL 82, and outputs it to the VCO 81. The 90 degree phase shifter 84 shifts the phase of the oscillation signal received from the VCO 81 by 90 degrees, and provides it to the mixer circuit 80.
Based on the oscillation signal received from the 90 degree phase shifter 84, the mixer circuit 80 converts the RF signal received from the variable gain amplifier 99 to a signal having an infrasonic frequency (hereinafter referred to as IF signal) ranging from a several MHz to several 10 MHz. Then, the mixer circuit 80 provides the signal thus converted to a low pass filter circuit (LPF) 85. The LPF 85 passes low-frequency components of the IF signal received from the mixer circuit 80 and provides them to a variable gain amplifier 86. The variable gain amplifier 86 amplifies the IF signal received from the LPF 85, and provides it to an A/D converter 87 in the demodulation circuit 93.
The A/D converter 87 converts the IF signal received from the variable gain amplifier 86 to a digital signal, and provides it to the demodulation circuit 88. The demodulation circuit 88 demodulates the digital IF signal received from the A/D converter 87 to a demodulated signal, and provides it to a decoding circuit 89. The decoding circuit 89 decodes the demodulated signal received from the demodulation circuit 88 to generate a decoded signal, and provides it to a deinterleave circuit 70.
The deinterleave circuit 70 rearranges the decoded signal received from the decoding circuit 89 so as to break up sequential errors of the signal, and reconstructs correct data using an error correction technique. For this purpose, the deinterleave circuit 70 stores the decoded signal in an SRAM 95 via a selection circuit 71 provided in an SRAM (Static Random Access Memory) control circuit 94.
The demodulation circuit 93 includes a decoding circuit 72. The decoding circuit 72 reads out from the SRAM 95 decoded signal data, which is reconstructed into correct data by the deinterleave circuit 70 using the error correction technique. The decoding circuit 72 then decodes the decoded signal data thus read out, and outputs it to the semiconductor test device 77 via an output terminal 63.
The demodulation circuit 93 further includes a PLL 73. The PLL 73 outputs a control signal to the A/D converter 87, the demodulation circuit 88, the decoding circuit 89, the deinterleave circuit 70, the decoding circuit 72, and the selection circuit 71.
The semiconductor integrated circuit 91 has input terminals 62, 61, 97, and 60. In order to control an SRAM, generally, a read/write switching signal, an address signal having a width of M bit, and a data signal having a width of N bit are required. In the semiconductor test device 77, a read/write switching signal, an address signal having a width of M bit, and a data signal having a width of N bit are supplied from the SRAM test interface 78 of the semiconductor test device 77 via the input terminals 62, 61, and 97, respectively, and provided to the SRAM 95 by the selection circuit 71. Further, a clock signal is supplied from the SRAM test interface 78 via the input terminal 60, and provided to the SRAM 95 by the selection circuit 71.
The demodulation circuit 93 further includes a demodulation circuit control register 74 and a serial communication circuit 75. The demodulation circuit control register 74 transmits control data concerning: the A/D converter 87, the demodulation circuit 88, the decoding circuit 89, the interleave circuit 70, and the decoding circuit 72, which are provided in the demodulation circuit 93. The control data is transmitted by serial communication performed by the serial communication circuit 75. Further, the demodulation circuit control register 74 transmits to a control register 76, provided in the high-frequency receiving circuit 92, test data which is supplied from the semiconductor test device 77 via the input terminal 64 and which is used to drive and test the VCO 81 and the PLL 82 both provided in the high-frequency receiving circuit 92.
The control register 76 of the high-frequency receiving circuit 92 provides the VCO 81 and the PLL 82 with the test data, received from the control register 74 by serial communication. The result of testing the high-frequency receiving circuit 92 is supplied as a test result signal to the semiconductor test device 77 via a test result output terminal 69, provided in the semiconductor integrated circuit 91. Specifically, the test result signal is outputted from a phase comparator of the PLL 82 via the test result output terminal 69. The test result signal indicates whether or not the VCO 81 oscillates a signal at a specific frequency.
FIG. 9 is a flow chart representing a process of testing the conventional semiconductor integrated circuit 91. First, the demodulation circuit 93 serving as a logic circuit is tested using an Automatic Test Pattern Generation (ATPG) method to detect an error of gates constituting a logic circuit (step S91), while the SRAM 95 of the demodulation circuit 93 is tested for its memory (Step S94). After both the test using the ATPG method and the test for the SRAM 95 are completed, a test for the PLL 73 of the demodulation circuit 93 (step S92) and then a test for the AID converter 87 of the demodulation circuit 93 (step S93) are performed. Further, the PLL 82 and the VCO 81 both constituting an analog circuit, i.e., the high-frequency receiving circuit 92, are tested to detect, for example, whether or not the VCO 81 oscillates a signal at a desirable frequency (step S95).
In the above conventional structure, however, the following problem may arise, for example, when testing with high accuracy whether the VCO oscillates a signal at a specific frequency. Test data used to test the frequency band of 1 GHz by sampling 100 points at an interval of 10 MHz is transmitted to the control register 76 of the high-frequency receiving circuit 92 from the control register 74 of the demodulation circuit 93. Specifically, the test data is transmitted by serial communication at a slow rate raging from several 10 kHz to several 100 kHz to the receiving end, i.e., the control register 76 provided in the high-frequency receiving circuit 92. Since the high-frequency receiving circuit 92 receives data in a frequency band ranging from several 100 MHz to several GHz, its register has a capacity of several bytes. Thus, it takes time for setting up the control register 76, requiring enormous time for testing the high-frequency receiving circuit 91.
The high-frequency receiving circuit 92 is constituted by an analog circuit, and the demodulation circuit 93 is constituted by a digital circuit. Since there has been no semiconductor test device capable of testing an analog circuit and a digital circuit simultaneously, a test for the high-frequency receiving circuit 92 and a test for the demodulation circuit 93 need to be performed separately. For example, the demodulation circuit 93 is tested first, and then the high-frequency receiving circuit 92 is tested. Tests of a logic circuit generally include a test using the ATPG method and a test for memory, which require more and more time according to increase in size of a circuit. Tests of an analog circuit also take time due to (i) time required for waiting until an analog circuit is stabilized, (ii) a high demand for improving accuracy of tests, and (iii) increased test items. Currently, the tests of the high-frequency receiving circuit 92 and the demodulation circuit 93 have been performed separately, which is disadvantageous in respect of test time.
Japanese Unexamined Patent Publication No. 152027/2004 (Tokukai 2004-152027, publication date: May 27, 2004) (Patent Document 1) discloses a method for testing a semiconductor chip incorporating a digital circuit including a microcomputer unit and a memory unit. However, Patent Document 1 is silent about a test for a semiconductor chip incorporating a high-frequency receiving circuit (analog circuit) and a demodulation circuit (digital circuit). Thus, the present invention is not suggested in Patent Document 1.
Japanese Unexamined Patent Publication No. 243791/2001 (Tokukai 2001-243791, publication date: Sep. 7, 2001) (Patent Document 2) (FIG. 5 and Paragraph [0047] of the specification) discloses a testing device which tests both an analog circuit and a digital circuit. In Patent Document 2, however, the analog circuit and the digital circuit are tested separately. Thus, the present invention is not suggested in Patent Document 2.